High Performance Loop Filter Design for Continuous-time Sigma-delta ADC

Abstract

Continuous-time (CT) sigma-delta (ΣΔ) analog-to-digital converters (ADCs) are widely used in wireless transceiver. Loop filter becomes a critical component in the implementation of high resolution large bandwidth CT ΣΔ ADC because it determines loop stability and defines quantization noise-shaping behavior of the ΣΔ modulator.

In this thesis, an extremely low power loop filter for 11-bit dynamic range 15MHz CT ΣΔ ADC is described. On the system level, a new local feedback structure which consists of a CT differentiator in cascade with an integrator is proposed to solve the problem of excess loop delay and eliminate the use of a power-hungry summing amplifier. Proposed continuous-time differentiator is demonstrated to make the whole ΣΔ loop more robust to delay variation and easier designed than previously published discrete-time differentiator. On the circuit level, two-stage operational amplifiers with new class-AB output stages are used to implement low-power active RC integrators. The proposed class-AB output stage is proven to be more linear than conventional one. The whole ΣΔ ADC circuit was designed, simulated and implemented in IBM 130nm CMOS technology. The designed loop filter including CT differentiator draws less than 3mA from 1.2V supply voltage.