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dc.contributor.advisorJimenez, Daniel A.
dc.creatorWang, Zhe
dc.date.accessioned2015-02-05T17:24:15Z
dc.date.available2016-08-01T05:30:17Z
dc.date.created2014-08
dc.date.issued2014-07-28
dc.date.submittedAugust 2014
dc.identifier.urihttp://hdl.handle.net/1969.1/153330
dc.description.abstractPrograms exhibit significant performance variance in their access to microarchitectural structures. There are three types of performance variance. First, semantically equivalent programs running on the same system can yield different performance due to characteristics of microarchitectural structures. Second, program phase behavior varies significantly. Third, different types of operations on microarchitectural structure can lead to different performance. In this dissertation, we explore the performance variance and propose techniques to improve the processor design. We explore performance variance caused by microarchitectural structures and propose program interferometry, a technique that perturbs benchmark executables to yield a wide variety of performance points without changing program semantics or other important execution characteristics such as the number of retired instructions. By observing the behavior of the benchmarks over a range of branch prediction accuracies, we can estimate the impact of a microarchitectural optimization optimization and not the rest of the microarchitecture. We explore performance variance caused by phase changes and develop prediction-driven last-level cache (LLC) writeback techniques. We propose a rank idle time prediction driven LLC writeback technique and a last-write prediction driven LLC writeback technique. These techniques improve performance by reducing the write-induced interference. We explore performance variance caused by different types of operations to Non-Volatile Memory (NVM) and propose LLC management policies to reduce write overhead of NVM.We propose an adaptive placement and migration policy for an STT-RAM-based hybrid cache and writeback aware dynamic cache management for NVM-based main memory system. These techniques reduce write latency and write energy, thus leading to performance improvement and energy reduction.
dc.format.mimetypeapplication/pdf
dc.language.isoen
dc.subjectPerformance Model
dc.subjectCache
dc.subjectDRAM
dc.subjectReplacement Policy
dc.subjectWirte-Induced Interference
dc.subjectNon-Volatile Memory
dc.titleImproving Processor Design by Exploiting Performance Variance
dc.typeThesis
thesis.degree.departmentComputer Science and Engineering
thesis.degree.disciplineComputer Science
thesis.degree.grantorTexas A & M University
thesis.degree.nameDoctor of Philosophy
thesis.degree.levelDoctoral
dc.contributor.committeeMemberGratz, Paul V.
dc.contributor.committeeMemberKim, Eun Jung
dc.contributor.committeeMemberTaylor, Valerie E.
dc.type.materialtext
dc.date.updated2015-02-05T17:24:15Z
local.embargo.terms2016-08-01
local.etdauthor.orcid0000-0002-9844-4173


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