dc.contributor.advisor | Mahapatra, Rabi N | |
dc.creator | Tripathy, Aalap | |
dc.date.accessioned | 2014-05-13T17:27:19Z | |
dc.date.available | 2015-12-01T06:31:21Z | |
dc.date.created | 2013-12 | |
dc.date.issued | 2013-12-06 | |
dc.date.submitted | December 2013 | |
dc.identifier.uri | https://hdl.handle.net/1969.1/151862 | |
dc.description.abstract | The increasing amount of information accessible to a user digitally makes search difficult, time consuming and unsatisfactory. This has led to the development of active information filtering (recommendation) systems that learn a user’s preference and filter out the most relevant information using sophisticated machine learning techniques. To be scalable and effective, such systems are currently deployed in cloud infrastructures consisting of general-purpose computers. The emergence of many-core processors as compute nodes in cloud infrastructures necessitates a revisit of the computational model, run-time, memory hierarchy and I/O pipelines to fully exploit available concurrency within these processors.
This research proposes algorithms & architectures to enhance the performance of content-based (CB) and collaborative information filtering (CF) on many-core processors. To validate these methods, we use Nvidia’s Tesla, Fermi and Kepler GPUs and Intel’s experimental single chip cloud computer (SCC) as the target platforms. We observe that ~290x speedup and up to 97% energy savings over conventional sequential approaches. Finally, we propose and validate a novel reconfigurable SoC architecture which combines the best features of GPUs & SCC. This has been validated to show ~98K speedup over SCC and ~15K speedup over GPU. | en |
dc.format.mimetype | application/pdf | |
dc.language.iso | en | |
dc.subject | GPGPU | en |
dc.subject | SCC | en |
dc.subject | Mapreduce | en |
dc.subject | semantic information filtering | en |
dc.subject | collaborative information filtering | en |
dc.subject | recommendation system | en |
dc.subject | many-core computing | en |
dc.subject | many-core programming models | en |
dc.subject | reconfigurable architectures | en |
dc.subject | System on chip (SoC) | en |
dc.title | High Performance Information Filtering on Many-core Processors | en |
dc.type | Thesis | en |
thesis.degree.department | Computer Science and Engineering | en |
thesis.degree.discipline | Computer Engineering | en |
thesis.degree.grantor | Texas A & M University | en |
thesis.degree.name | Doctor of Philosophy | en |
thesis.degree.level | Doctoral | en |
dc.contributor.committeeMember | Choi, Gwan S | |
dc.contributor.committeeMember | Choe, Yoonsuck | |
dc.contributor.committeeMember | Caverlee, James | |
dc.type.material | text | en |
dc.date.updated | 2014-05-13T17:27:19Z | |
local.embargo.terms | 2015-12-01 | |