Abstract
Historically, data communication protocols have been implemented in software; however, with transmission rates faster than clock cycles in most computers, future protocols are expected to be implemented in hardware. Furthermore, protocol processing can become a substantial part of all processing in a host computer. If protocol processing can be implemented by a set of inexpensive VLSI circuits, this would reduce the total system cost. In this thesis, the PSi Connection Processor for the Xpress Transfer Protocol is designed. The implementation is based on the finite state machines in revision 3.4. While reviewing the state machines 7 it became clear that they would require modifications to ensure that they will behave as one must assume was intended. This view was supported by discussions with Greg Chesson, who advised not taking the state machines too literally, but rather use them mainly as a guide for implementation. The product of the decomposition and partitioning process of the XTP protocol is a reflection of the characteristics of the protocol. The modifications were therefore limited to changes within each state machine. To ensure the integrity of the implementation, no alterations were conducted that substantially effects their interaction and execution. The implementation in the Verilog Hardware Description Language may be used to obtain an area estimate of the Connection Processor.
Brudeseth, Rolf (1994). Design of the PSI connection processor for the Xpress transfer protocol. Master's thesis, Texas A&M University. Available electronically from
https : / /hdl .handle .net /1969 .1 /ETD -TAMU -1994 -THESIS -B888.